Digital-to-Analog conversion is a crucial technique in embedded systems when microcontrollers need to produce real-world analog signals such as audio, control voltages, or test waveforms.
The ATmega16 does not contain a dedicated built-in DAC channel, but there are several practical ways to create analog outputs using AVR hardware or external chips.
The three widely used approaches are: wired resistor networks (R-2R ladder), filtered PWM output (microcontroller PWM + low-pass filter), and dedicated external DAC chips (SPI/I²C DAC such as MCP4921 / MCP4922).
Each approach has its trade-offs in terms of resolution, linearity, speed, cost and simplicity.
In this long-form guide we will study DAC principles, compare options, show pinouts and features for a common external DAC, and provide detailed, ready-to-use C code and wiring diagrams for ATmega16.
You will learn how to make sine, triangle and square waveforms, how to choose sampling rate and filter characteristics, and how to drive an external DAC using the SPI peripheral on ATmega16.
Example code includes an R-2R parallel port output, PWM-with-filter routine using Timer1, and SPI code to feed a 12-bit DAC chip.
After this article you will be able to pick the method that fits your project — low-cost R-2R for slow signals, PWM for medium fidelity, or an external DAC for high quality analog generation.
What is a DAC and key features
A digital-to-analog converter (DAC) transforms a binary numeric value into a corresponding voltage (or current) level.
Important DAC characteristics are resolution (bits), update/sample rate, linearity (INL/DNL), monotonicity, output range (0–Vref, ±Vref), settling time, and interface (parallel, SPI, I²C).
For waveform generation you must consider sample rate and filter design — Nyquist requires sample rate > 2× highest frequency; in practice use much higher rates and low-pass filtering to remove stair-step quantization and PWM carrier components.
Common DAC approaches with ATmega16 (summary)
| Method | Pros | Cons | Use-case |
|---|
| R-2R ladder (parallel GPIO) | Very simple, low cost, deterministic latency | Limited resolution if port size small, requires many GPIOs, non-ideal resistor matching | Low-frequency analog signals, labs and demos |
| PWM + low-pass filter | Uses single pin, easy, flexible resolution by software averaging | Requires careful filtering, carrier ripple, limited bandwidth | Audio-low freq control (with filtering), simple analog outputs |
| External DAC (SPI/I²C, e.g. MCP4921) | High resolution, fast, accurate, professional results | Additional chip, cost, SPI wiring | Precision waveform, audio, industrial control |
Note: For real analog use prefer an external DAC (12-bit or higher). For prototyping and educational experiments an R-2R ladder or PWM solution is fine.
External DAC example — MCP4921 (12-bit, SPI)
MCP4921 is a popular single-channel 12-bit DAC with SPI interface and output buffer/gain options.
It accepts a 16-bit command word (control bits + 12-bit data) over SPI and produces an output voltage on its analog output pin proportional to the 12-bit input with respect to Vref.
Using MCP4921 with ATmega16 lets you create high quality waveforms if you update the DAC at an adequate sample rate and use a reconstruction filter (simple RC or higher-order active filter).
MCP4921 typical pinout (for wiring)
| Pin | Name | Function |
|---|
| 1 | Vout | Analog output (connect to filter / buffer) |
| 2 | VREF | Reference voltage (tie to +Vref, e.g. 5V or stable reference) |
| 3 | AGND | Analog ground |
| 4 | LDAC | Load DAC (active low; can tie low for immediate update) |
| 5 | CS | Chip Select (active low) — use MCU GPIO |
| 6 | SCK | SPI clock input |
| 7 | SDI / MOSI | SPI data input |
| 8 | VDD | Power supply (typically 5V) |
Wiring summary for MCP4921 & ATmega16
- ATmega16 MOSI (DORD) → MCP4921 SDI
- ATmega16 SCK → MCP4921 SCK
- ATmega16 any GPIO as CS → MCP4921 CS
- MCP4921 VREF → precise reference (e.g. 5.0V or external ref)
- Vout → simple RC filter (for smoothing) → output measurement
- Common grounds between MCU and DAC must be connected
SPI DAC code (ATmega16) — continuous sine output example
Below is a compact example demonstrating SPI setup and sending 12-bit samples to an external DAC. The code uses a small sine lookup table (example 32 samples) and updates the DAC at a chosen sample rate using Timer1 compare interrupt. Adjust table size and timer delay to get desired frequency and sample rate.
#ifndef F_CPU
#define F_CPU 16000000UL
#endif
#include <avr/io.h>
#include <avr/interrupt.h>
#include <util/delay.h>
#include <stdint.h>
#define DAC_CS_PORT PORTB
#define DAC_CS_DDR DDRB
#define DAC_CS_PIN PB4
const uint16_t sine_table[32] = {
2048,2447,2831,3185,3495,3750,3939,4056,
4095,4056,3939,3750,3495,3185,2831,2447,
2048,1649,1265,911,601,346,157,40,
0,40,157,346,601,911,1265,1649
};
static inline void spi_init_master(void) {
DDRB |= (1<<PB4)|(1<<PB5)|(1<<PB7);
DDRB &= ~(1<<PB6);
SPCR = (1<<SPE) | (1<<MSTR);
SPSR = (1<<SPI2X);
}
static inline void dac_cs_low(void) { DAC_CS_PORT &= ~(1<<DAC_CS_PIN); }
static inline void dac_cs_high(void) { DAC_CS_PORT |= (1<<DAC_CS_PIN); }
static uint8_t spi_transfer(uint8_t data) {
SPDR = data;
while (!(SPSR & (1<<SPIF)));
return SPDR;
}
void dac_write_12bit(uint16_t value) {
uint8_t high = 0x30 | ((value >> 8) & 0x0F);
uint8_t low = value & 0xFF;
dac_cs_low();
spi_transfer(high);
spi_transfer(low);
dac_cs_high();
}
volatile uint8_t idx = 0;
ISR(TIMER1_COMPA_vect) {
dac_write_12bit(sine_table[idx]);
idx = (idx + 1) & 0x1F;
}
int main(void) {
DAC_CS_DDR |= (1<<DAC_CS_PIN);
DAC_CS_PORT |= (1<<DAC_CS_PIN);
spi_init_master();
TCCR1B = (1<<WGM12) | (1<<CS10);
OCR1A = 1999;
TIMSK |= (1<<OCIE1A);
sei();
while (1) {
_delay_ms(500);
}
}
Notes on SPI DAC code
The control nibble used when building the high byte depends on the DAC you choose. Consult the DAC datasheet for exact control bits (buffering, output gain, shutdown).
The sample rate and table length determine the output waveform frequency: waveform_freq = sample_rate / table_length. For a 32-sample table and 8 kHz sample_rate the sine frequency is 8000/32 = 250 Hz.
R-2R ladder DAC (discrete resistor network)
An R-2R ladder uses matched resistors arranged as a binary-weighted network. Each bit of a digital word drives a resistor branch; the ladder sums currents to produce an analog voltage proportional to the binary value. For an 8-bit R-2R you will need 8 digital outputs (one per bit) and 9 resistors (R and 2R values). R-2R is useful for low-cost experiments; accuracy depends on resistor tolerance and layout. Use tight tolerance resistors (0.1% or 0.5%) for better linearity.
R-2R practical wiring & code example (8-bit)
Connect PortA (PA0..PA7) to the R-2R ladder inputs. The ladder output (VO) goes through a small RC filter to smooth steps and then to a buffer op-amp if you need low source impedance.
/* R-2R DAC example — ATmega16
Outputs 8-bit samples on PORTA. Use small RC filter after ladder.
*/
#include <avr/io.h>
#include <util/delay.h>
const uint8_t sine8[32] = {
128,176,218,246,255,246,218,176,
128,80,38,10,0,10,38,80,
128,176,218,246,255,246,218,176,
128,80,38,10,0,10,38,80
};
int main(void) {
DDRA = 0xFF; // PORTA as output to R-2R ladder
while(1) {
for(uint8_t i=0;i<32;i++){
PORTA = sine8[i];
_delay_ms(2); // sample delay
}
}
}
PWM DAC using Timer1 and low-pass filter
PWM DAC uses a high-frequency pulse-width-modulated output whose average after a low-pass filter equals the desired analog voltage. Benefits: uses one pin, flexible effective resolution (via oversampling and filtering). Drawbacks: needs a sufficiently high PWM carrier and good filter design for low ripple and desired bandwidth.
PWM code example (8-bit waveform)
/* PWM DAC example — ATmega16, Timer1 8-bit Fast PWM on OC1A (PD5)
Use an RC filter (e.g. R=4.7k, C=10nF) on OC1A pin to get analog voltage.
*/
#include <avr/io.h>
#include <util/delay.h>
const uint8_t sine8[32] = {
128,176,218,246,255,246,218,176,
128,80,38,10,0,10,38,80,
128,176,218,246,255,246,218,176,
128,80,38,10,0,10,38,80
};
int main(void) {
/* Configure PD5 (OC1A) as output */
DDRD |= (1< high carrier */
TCCR1A = (1< controls output frequency
}
}
}
Filter design notes
For R-2R and PWM outputs you must use a reconstruction filter. A simple RC low-pass filter attenuates carrier and smooths steps. Choose cutoff fc << PWM carrier but fc > desired signal bandwidth. Example: for audio up to 3 kHz choose carrier 64 kHz and fc ≈ 6 kHz. For test signals you may use a passive RC (R=4.7k, C=10nF -> fc ≈ 3.4 kHz) or better use 2nd-order active filters for less ripple.
Waveform visualization (sine, triangle, square)
Practical tips & troubleshooting
- Always common-ground MCU and DAC supplies to avoid level shifts or no output.
- Use ceramic or electrolytic decoupling close to DAC VCC/VREF pins to stabilize reference.
- For R-2R ladders use matched resistors (0.1% or 0.5%) to improve linearity and monotonicity.
- When using PWM, increase carrier frequency and use a suitable RC/active filter to reduce ripple.
- Check timing when using SPI: ensure CS toggles properly around the SPI transfer so DAC latches update correctly.
Conclusion
Generating analog waveforms from ATmega16 is very achievable with several methods. For hobby and learning, R-2R ladders and PWM-with-filter are inexpensive and instructive. For reliable, high-quality analog signals, use an external SPI/I²C DAC and a proper reconstruction filter. Choose resolution and sample rate according to the signal frequency you need, and always pay attention to grounding, decoupling and resistor tolerances. The examples here provide a solid foundation — you can adapt table sizes, timer settings and filters to create audio, control voltages or test signals for your projects.
